Electrostatic discharge (ESD) projection circuits may provide ESD protection in a number of applications. A variety of different ESD devices are available for use in circuits of this kind. One example of such a device is the grounded gate NMOS (ggNMOS) transistor. An example of a ggNMOS device is schematically illustrated in FIG. 1.
The device includes a source 4, a gate 8 and a drain 6 in a semiconductor substrate. In particular, the source 4 and drain 6 may be provided in a p-well 14 in the substrate. As the device is an NMOS device, the source 4 and drain 6 are themselves n-doped (N+). A p-doped (P+) contact region 2 may also be provided to allow electrical connection to the body of the substrate. The p-doped contact region 2, the source 4 and the gate 8 may be electrically connected together to a common reference potential via a common bond pad 12, which forms a cathode of the device. The common reference potential is typically ground. The drain 6 is connected to a contact pad 16 which forms an anode of the device.
The ggNMOS transistor shown in FIG. 1 operates as a parasitic npn bipolar transistor in use. In particular, the drain 6 of the ggNMOS transistor acts as the collector, the body of the substrate in the p-well 14 acts as the base, and the source of the ggNMOS transistor acts as the emitter. The bipolar transistor is schematically illustrated using the reference sign 10 in FIG. 1. During an ESD event, the collector-base junction (the junction between the drain 6 and the body region of the ggNMOS transistor in the p-well 14) becomes reverse biased and avalanche breakdown at that junction occurs. The breakdown current flows to ground, which forms a potential across the resistor 18 (which is schematically representative of the base resistance of the parasitic npn). This causes a positive voltage to form across the base-emitter junction (forward bias) triggers the parasitic npn transistor.
FIGS. 2 and 3 illustrate the layouts of two ggNMOS transistors that are known in the art, and which may be used in a device of the kind explained above in relation to FIG. 1.
The device in FIG. 2 includes an active region 25 having a source 20, a gate 22 and a drain 30. The device in FIG. 2 is a fully silicided device. Accordingly, the source 20, drain 30 and also an upper portion of the gate poly of the gate 22 all comprise silicide. Silicide is itself a commonly used material in the field of semiconductor device manufacture, and various silicidation processes are also well known in the art. A plurality of source contacts 12 are provided on the source 20 and a plurality of drain contacts 16 are provided on the drain 30.
A fully silicided device of the kind shown in FIG. 2 can suffer from device failure due to a phenomenon known as hot spotting. This is a well-known phenomenon in which current flowing from the source to the drain naturally finds the path of lowest resistance within the device and concentrates there. The high current density in this region eventually causes the device to fail.
The example device shown in FIG. 3 also includes an active region 25 having a source 20, a drain 30 and a gate 22. Again, the device has a plurality of source contacts 12 and a plurality of drain contacts 16. In the example of FIG. 3, the device includes a non-silicide region 35. The non-silicide region 35 may be formed using a protection mask during manufacture to prevent an area of the active region 25 of the device from being silicided during the silicidation process. The non-silicide region 35 in FIG. 3 is represented by the cross-hatched area. The area of the active region 25 outside the non-silicide region 35 (which is not cross-hatched in FIG. 3) is silicided.
In this example, the sheet resistance of the non-silicided region 35 of the device provides a ballast resistance which can inhibit an overly large current from flowing within the device, thereby helping to prevent the hot spotting phenomenon noted above in respect of the fully silicided device of FIG. 1. However, a consequence of the addition of the non-silicide region 35 is that the size of the active region 25 of the device increases (this is represented by the arrow labelled L in FIG. 3). The increase in size is typically 2 L, which includes the length of the non-silicide region 35 on either side of the gate 22. It will be appreciated that a substantial increase in the size of the device is generally not a desirable consequence in a number of applications in which space is at a premium.
WO2003/094242 describes a field effect transistor (FET) which has an active area in a semiconductor body, a channel formed in the active area, a source diffusion zone and a drain diffusion zone alternating with each other in the active area, a source diffusion zone being separated from a drain diffusion zone by the channel. Each source diffusion zone has a source contact and each drain diffusion zone has a drain contact.